Printed circuits are becoming increasingly more complex and inaccessible for traditional testing methods such as, for example, test clips, probes and bed-of-nails fixtures. Increased degrees of miniaturization has reduced accessibility for testing and has necessitated development of methods for internal and boundary scan architecture. IEEE has specified voluntary standards for low speed internal and boundary testing to address this problem. The standard allows customers to purchase chips from various manufacturers and find them all to be compatible.
The IEEE standard defines test logic that can be included in an integrated circuit to provide standardized approaches to testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate; testing the integrated circuit itself; and observing or modifying circuit activity during the component's normal operation at a test speed.
The test logic consists of a boundary scan register and other building blocks accessed through a Test Access Port (TAP). The circuitry defined by the standard allows test instructions and associated test data to be fed into a component and, subsequently, allows the results of execution of such instructions to be read out. All information (instructions, test data, and test results) is communicated in a serial format. The sequence of operations can be controlled by a bus master, which can be either an automatic test equipment (ATE) or a component that interfaces to a higher-level test bus as a part of a complete system maintenance architecture. Control is achieved through signals applied to Test Mode Select (TMS) and Test Clock (TCK) inputs of the various components connected to the bus master. Starting from an initial state in which the test circuitry defined by this standard is inactive, a typical sequence of operations would be as follows:
The first step would be, in general, to load serially into the component, the instruction code for a particular operation to be performed. The test logic defined by the standard is designed such that the serial movement of instruction information is not apparent to those circuit blocks whose operation is controlled by the instruction. The instruction applied to these blocks changes only on completion of the shifting (instruction load) process.
Once the instruction has been loaded, the selected test circuitry is configured to respond. In some cases, however, it is necessary to load data into the selected test circuitry before a meaningful response can be made. Such data are loaded into the component serially in a manner analogous to the process used previously to load the instruction. The movement of test data has no effect on the instruction present in the test circuitry.
The test instruction is executed and then, based where necessary on supplied data, the results of the test can be examined by shifting data out of the component to or through the bus master. In cases where the same test operation is to be repeated but with different data, new test data can be shifted into the component while the test results are shifted out. There is no need for the instruction to be reloaded.
Operation of the test circuitry may proceed by loading and executing several further instructions in a manner similar to that described above and or conclude by returning the test circuitry and, where required, on-chip system circuitry, to its initial state.
Storey and McWilliam ("A test methodology for high performance MCMs", Thomas M. Storey, Bruce McWilliam, Journal of Electronic Testing: Theory and Applications, vol. 10, pp 109-118, 1997) show how to test interconnect and glue logic between integrated circuits using a specific boundary scan technique (i.e. LSSD-Level Sensitive Scan Design). This technique allows testing of delay faults and has good diagnostic resolution. The problems with this method are: 1) it is incompatible with the IEEE 1149.1 standard which is the most commonly accepted test architecture in the industry. Therefore, even for low speed testing, non-standard test methodology and equipment are required; 2) very few components are designed using this clocking methodology; and 3) it is very difficult to augment to support Built-In Self-Test at the board level.
Zorian and Bederr ("An Effective Multi-Chip BIST Scheme", Yervant Zorian, Hakim Bederr, Journal of Electronic Testing: Theory and Applications, vol. 10, pp 87-95, 1997) teach us how to test interconnect only at high-speed. However 1) their solution cannot handle glue logic at all; 2) the diagnostic resolution is not sufficient (output data is compacted at the outputs of the various chips--for instance if the signature collected in the ODC-IO of a chip is good and the signature of ODC-IO of the following chip is bad, then one can conclude that the fault is in the interconnects between the chips, and not in the chips). It only allows one to determine that at least one signal was too slow in a bus (group) of signals; 3) the timing of enable signals cannot be tested because fixed configurations are used; and 4) multi-cycle paths are not supported (i.e. signals must propagate from one integrated circuit to the other within a single clock cycle of the high speed system clock). This is not always acceptable; and 5) they acknowledge that the test registers of different integrated circuits must be synchronized, but do not explain how. This is a difficult problem to resolve.